1. Field of the Invention
The present invention relates generally to memory devices used in computerized control systems and more particularly to an improved first-in-first-out (FIFO) buffer having bidirectional input/output ports and on-chip parity generation and checking circuitry operative to save space and power and reduce component count and manufacturing cost in typical applications.
2. Description of the Prior Art
Digital electronic first-in-first-out (FIFO) buffers are typically used by electronic system designers to alleviate "bottleneck" conditions that arise during communication between two or more digital systems of widely differing operating frequencies (a computer and its peripherals, for example). These FIFOs operate by "buffering", or temporarily storing, data from the transmitting system until the receiving system is ready to accept the data.
Small bipolar FIFO buffers (typically, 16 words by 4 bits) emerged in the late 1970's. The architecture then was primarily shift-register oriented with a unidirectional data bus. Even with bipolar technology, these FIFOs had relatively slow data transfer rates, typically less than 5 Mhz. Since that time, CMOS technology has brought to market many larger and faster parallel FIFOs. The mainstream products on the market now are parallel FIFOs with typical densities of 1K.times.9 to 4K.times.9. With CMOS technology, the majority of these devices have access times in the 25 ns to 35 ns range. However, modern 32-bit CISC and RISC microprocessor systems, with system bus frequencies of 40 MHz to 50 MHz or higher, dictate a need for buffers with faster access times and the ability to support wider data buses. Further, at these high speeds, retaining high data integrity has become a critical problem. System designers have typically included external parity generating and checking hardware to insure data integrity. However, this is a less than ideal solution, because it increases data path length, power consumption, and component space required, all of which are at a premium in modern designs.
An additional concern for system designers is the "bottleneck" condition that arises between digital systems with different bus widths. For example, many peripherals still operate on an 8 bit data bus, while most modern microprocessors have a bus width of 16 bits or larger. This is typically handled by forcing the microprocessor to communicate over only a portion of its bus. This has the effect of drastically increasing the time required by the microprocessor to transmit information.
For many FIFO applications, system designers have been forced to use multiple parallel FIFO chips to implement two buffers, one to receive and one to send data. The modern bidirectional first-in-first-out (BiFIFO) buffer was developed in response to this need. Such a device utilized two bidirectional ports, thus allowing it to buffer data in either direction. There are two classes of these BiFIFOs: single-core and dual-core.
The single-core, half-duplex devices are built upon a single, unidirectional FIFO core with bidirectional input/output ports; as such, it supports buffering in only one direction at a time. A Cypress Semiconductor component data sheet discloses such a single-core bidirectional FIFO, designated part number CY7C439. However, this device does not address the problems of data integrity or communication between systems with different bus widths. In addition, its minimum access time of 30 ns is insufficient for some modern high speed applications.
The dual-core, full-duplex devices, in contrast, include two unidirectional FIFO cores oriented in opposite directions, allowing buffering of data in both directions at the same time. However, because these devices employ two FIFO cores, they consume much more power than the single-core devices. A Sharp component data sheet discloses such a dual-core bidirectional FIFO, designated part number LH5420.